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Logic synthesis is a process where abstract description of a digital circuit usually in HDL (Hardware Description Language) language is converted into gates or other basic logic elements. The abstract description must not exceed abilities of used synthesis tool. In order to achieve that goal a set of rules and constraints was defined, which must be strictly followed while designing circuit in HDL language. The HDL code consistent with all the rules and constrains is named RTL (Register Transfer Level) code. RTL code defines functionality of a design on the level of logic operations performed on signals transferred between registers. The basis RTL rules are gathered in IEEE Std 1076.6-1999 standard. However, synthesis tools vendors constantly rise the abstraction level outside the scope defined in IEEE standard in their modern tools.
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