Digital Logic and Electronic Systems
Design Company

Technical Background

  VHDL Language

  Logic Synthesis


VHDL Language (VHSIC Hardware Description Language) was originally developed as a project financed by US Department of Defense. It was language designed to write documentation for complex digital circuits. Simulation and logic synthesis tools transformed quickly VHDL into design and verification language. It is now commonly used by ASIC and FPGA designers. It allows faster and easier development of digital circuits comparing to previously used schematics. VHDL can be also used to write testbenches that verify design functionality. Verilog-HDL language is the main VHDL competitor. Verilog-HDL was originally developed by industry and it seems to be popular in United States. However, VHDL is more frequently used in Europe. Both the languages became IEEE standards. They are constantly modified and improved. Most of the recent improvements are focused on verification. The HDL languages are extended with constructs previously used in object oriented programming only.


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